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 NCS6416 Low-V oltage, Bus-Contr olled Video Matrix Switch
Description
The main function of the NCS6416 is to switch 8 video input sources to the 6 outputs. The NCS6416 operates with a low 5 V power supply. Each output can be switched to only one of the inputs, whereas any single input may be connected to several outputs. All switching possibilities are controlled through the I2C bus inputs.
Features
http://onsemi.com MARKING DIAGRAMS*
20
20 1
NCS6416 AWLYYWWG
* 20 MHz Bandwidth * 5 V Operating Voltage * Cascadable with another NCS6416 (Internal Address can be changed * * * * * * * *
by Pin 7 Voltage) 8 Inputs (CVBS, RGB, Chroma, ...) 6 Outputs with 150 W Output Driving Capability Possibility of Chroma Signal for each Input by Switching off the Clamp with an External Resistor Bridge Bus Controlled 6 dB Gain between any Input and Output -65 dB Crosstalk at 5 MHz Full ESD Protection These are Pb-Free Devices
SO-20 WB DW SUFFIX CASE 751D A WL YY WW G
1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
INPUT1 1 DATA1 2 INPUT2 3 CLOCK 4 INPUT3 5 INPUT4 6 PROG 7 INPUT5 8 VCC 9 INPUT6 10
20 INPUT8 19 VCCO 18 OUTPUT6 17 OUTPUT5 16 OUTPUT4 15 OUTPUT3 14 OUTPUT2 13 OUTPUT1 12 GND 11 INPUT7
ORDERING INFORMATION
Device NCS6416DWG NCS6416DWR2G Package SO-20 (Pb-Free) SO-20 (Pb-Free) Shipping 38 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2007
1
June, 2007 - Rev. 0
Publication Order Number: NCS6416/D
NCS6416
OUTPUT6 OUTPUT4 OUTPUT2 OUTPUT5 OUTPUT3 OUTPUT1 GND 18 17 16 15 14 13 12
INPUT1
1
INPUT2
3
INPUT3
5
INPUT4
6
INPUT5
8
INPUT6
10
INPUT7
11
INPUT8
20
Bus Decoder NCS6416 2 DATA 7 PROG 4 CLOCK 9 VCC 19 VCCO
Figure 1. Block Diagram
The main function of the NCS6416 is to switch 8 video input sources to the 6 outputs. Each output can be switched to only one of the inputs, whereas any single input may be connected to several outputs. The lowest level of each signal is aligned on each input (bottom of sync pulse for CVBS or Black Level for RGB signals). Each output is able to drive a 150 W load. The nominal gain between any input and output is 6 dB. For Chroma signals, the clamp is switched off by forcing an external 2.5 V DC resistor bridge on the input. Each input
can be used as a normal input or as a Chroma input (with external resistor bridge). All the switching possibilities are changed through the I2C bus. The switches configuration is defined by words of 16 bits: one word of 16 bits for each output channel. So, 6 words of 16 bits are necessary to determine the starting configuration upon power-on (power supply: 0 to 5 V). But a new configuration needs only the words of the changed output channels.
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NCS6416
Table 1. ATTRIBUTES
Characteristics ESD Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index: 28 to 34 Human Body Model Machine Model Value 2 kV 200 V Level 3 UL 94 V-0 @ 0.125 in.
1. For additional information, see Application Note AND8003/D
Table 2. MAXIMUM RATINGS
Parameter Power Supply Voltage Output Driver Power Supply Operating Temperature Range Storage Temperature Range Thermal Resistance, Junction-to-Air SO-20 Symbol VCC VCCO TA Tstg qJA Rating 6 6 0 to +70 -60 to +150 30 to 35 Unit V V C C C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 3. DC & AC Characteristics (TA = 25C, VCC = 10 V, RL = 10 kW, CL = 3 pF)
Symbol VCC VCCO ICC INPUTS Signal Amplitude (CVBS signal) (Note 2) Input Current (Per Output Connected) DC Level (Bottom of Sync Pulse) DC Level Shift (0C to 70C) (Note 2) RIN CIN OUTPUTS Dynamic Range (VIN = 1 VPP) (Note 2) Output Impedance (Note 2) AV BW Gain (Note 2) Bandwidth (Note 2) -1 dB Attenuation -3 dB Attenuation Differential Gain Error (Note 2) Differential Phase Error (Note 2) Crosstalk (f = 5 MHz) (Note 2) DC Level (Bottom of Sync Pulse) Continuous Output Current (Note 2) I2C BUS INPUT: DATA, CLOCK AND PROG Threshold Voltage (Note 2) 2. Guaranteed by design and/or characterization. 1.5 2 3 V 0.2 20 5.5 7 1.9 2.0 1 6.0 15 20 0.5 1.5 -65 0.3 -60 0.4 % dB V mA 6.5 2.1 VPP W dB MHz Input Resistance (Note 2) Input Capacitance (Note 2) 1.25 1.0 1 1.35 5 1 2 3 1.45 100 VPP mA V mV MW pF Supply Voltage Output Driver Power Supply Power Supply Current (No Load) Parameter Min 4.75 4.75 20 Typ 5.0 5.0 30 Max 5.25 5.25 40 Unit V V mA
DG DP
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NCS6416
Table 4. I2C BUS CHARACTERISTICS
Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Clock Low Period (Note 4) Clock High Period (Note 4) Data Setup Time (Note 4) Data Hold Time (Note 4) Setup Time from Clock High to Stop (Note 4) Start Setup Time following a Stop (Note 4) Start Hold Time (Note 4) Start Setup Time following Clock Low to High Transition (Note 4) 4.7 4.0 250 0 4.0 4.7 4.0 4.7 340 ms ms ns ns ms ms ms ms Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance (Note 3) Input Risetime (Note 3) Input Falltime (Note 3) Low Level Output Voltage Output Falltime (Note 3) Load Capacitance (Note 3) 1.5 V to 3 V 3 V to 1.5 V IOL = 3 mA 3V to 1.5 V VI = 0 to VCC -0.3 3.0 -10 +1.5 VCC +0.5 +10 10 1000 300 0.4 250 400 V V mA pF ns ns V ns pF Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency (Note 3) Input Risetime (Note 3) Input Falltime (Note 3) Input Capacitance (Note 3) 1.5 V to 3 V 3 V to 1.5 V VI = 0 to VCC -0.3 3.0 -10 0 +1.5 VCC +0.5 +10 100 1000 300 10 V V mA kHz ns ns pF Parameter Test Conditions Min Max Unit
3. Guaranteed by design and/or characterization. 4. Functionality guaranteed by design and/or characterization.
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NCS6416
Bus Selections
The I2C chip address is defined by the first byte. The second byte defines the input/output configuration.
Table 5. CHIP ADDRESS BYTE (1ST BYTE OF TRANSMISSION)
HEX 86 06 NOTE: Input/Output Selection Byte (2nd BINARY 1000 0110 0000 0110 byte of transmission) Comment When PROG pin is connected to Ground When PROG pin is connected to VCC
Table 6. I2C BUS OUTPUT SELECTIONS
Output Address (MSB) 00000 00100 00010 00110 00001 00101 00011 00111 Input Address (LSB) XXX XXX XXX XXX XXX XXX Pin 18 Pin 14 Pin 16 Not Used Pin 17 Pin 13 Pin 15 Not Used Selected Output Output is selected by the 5 MSBs
Table 7. I2C BUS INPUT SELECTIONS
Output Address (MSB) 00XXX 00XXX 00XXX 00XXX 00XXX 00XXX 00XXX 00XXX Input Address (LSB) 000 100 010 110 001 101 011 111 Pin 5 Pin 8 Pin 3 Pin 20 Pin 6 Pin 10 Pin 1 Pin 11 Selected Input Input is selected by the 3 LSBs
Example: 0010 0101 (Binary) or 25 (Hex) connects Pin 10 (input) to Pin 14 (output)
SDA
tBUF tLOW tSU.DAT
SCL tHD.STA SDA tSU.STA tR tHD.DAT tHIGH tF tSU.STO
Figure 2.
I2 C
Bus Timing Diagram
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NCS6416
VCCO + 75 W Z = 75 W +To Switch Matrix ESD Protection Input Buffer NCS6416 DC Video Output 75 W
Pins 1, 3, 5, 6, 8, 10, 11 and 20 Video Inputs
Input Clamp
Video Inputs
75 W
Figure 3. Input Configuration
Figure 4. Output Configuration
Pins 2, 4, 7 I2C Bus Inputs Input Buffer
I2C Decode Logic
ESD Protection
ACK
*For Pin 2 (SDA)
Figure 5. Bus I/O Configuration
USING A SECOND NCS6416 The programming input pin (PROG) allows two NCS6416 circuits to operate in parallel and to select them independently through the I2C bus by modifying the address byte. Consequently, the switching capabilities are doubled, or can be cascaded as shown in Figure 6.
NCS6416 SDA/SCL Logical 0" MCU Video Inputs PROG Video Outputs
NCS6416 SDA/SCL Logical 1" Video Inputs PROG Video Outputs
Figure 6. Cascaded NCS6416
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NCS6416
TYPICAL APPLICATION DIAGRAM NCS6416 is suited for single supply system, running on a single +5 V supply. It can drive a 150 W video output due to the built-in low impedance and high current video output stage. The high quality of the output stage and excellent
Additional Video Inputs
linearity provides video signal comparable to broadcast studio quality signals. The layout is not as critical to the design and it can be easily realized on a single sided board.
18 17 16 15 14 13 Output 6 Security Video Interface Outpu 1
Screen
Satellite TV receiver circuit
1 Input 1 3 5 6 8 10 11 20 Input 8
VCR
Additional Video Outputs
SDA
Prog
HDTV Receiver circuit
VCCO
Microcontroller
Figure 7. Typical Application Diagram
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SCL
NCS6416
Bus Decoder
NCS6416
VCCO = +5V 100mF C10 C1 R1 75W 100W C2 Input 2 R3 75W SCL Input 3 C3 R5 75W Input 4 R6 75W VCC = +5V C6 Input 5 R7 75W C7 Input 6 R8 75W VCC = +5V C9 10mF C8 100nF 100nF 9 VCC 10 INPUT6 INPUT7 R11 75W GND 11 C13 100nF Input 7 100nF 8 INPUT5 7 C4 100nF 6 R4 100W 4 R2 2 DATA INPUT2 VCCO OUTPUT6 18 100nF 1 20 19 C12 10mF C11 100nF R9 R10 75W R11 75W R12 75W R13 75W R14 75W R15 75W 75W Z = 75 W 75W Z = 75 W 75W Z = 75 W 75W Z = 75 W 75W Z = 75 W 75W Output 2 Output 3 Output 4 Output 5 Output 6 Input 8
Input 1
INPUT1
INPUT8
SDA
100nF 3
CLOCK
OUTPUT5
17 16 15
100nF 5
INPUT3
OUTPUT4
INPUT4
OUTPUT3 14 OUTPUT2 13 OUTPUT1 12
PROG
Output 1
Figure 8. Typical Application Circuit
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NCS6416
PACKAGE DIMENSIONS
SO-20 WB CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
h
B
S
A
SEATING PLANE
18X
e
A1
T
C
DIM A A1 B C D E e H h L q
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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NCS6416/D


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